Verilog File IO Operations

Data Types   Verilog Syntax   Verilog Data types   Verilog Scalar/Vector   Verilog Arrays

Building Blocks   Verilog Module   Verilog Port   Verilog Module Instantiations   Verilog assign statements   Verilog assign examples   Verilog Operators   Verilog Concatenation   Verilog always block   Combo Logic with always   Sequential Logic with always   Verilog initial block   Verilog in a nutshell   Verilog generate

Behavioral modeling   Verilog Block Statements   Verilog Assignment Types   Verilog Blocking/Non-blocking   Verilog Control Flow   Verilog if-else-if   Verilog Conditional Statements   Verilog for Loop   Verilog case Statement   Verilog Functions   Verilog Tasks   Verilog Parameters   Verilog `ifdef `elsif   Verilog Delay Control   Verilog Inter/Intra Delay   Verilog Hierarchical Reference   Verilog Coding Style Effect

Gate/Switch modeling   Gate Level Modeling   Gate Level Examples   Gate Delays   Switch Level Modeling   User-Defined Primitives

Simulation   Verilog Simulation Basics   Verilog Testbench   Verilog Timescale   Verilog Scheduling Regions   Verilog Clock Generator

System Tasks and Functions   Verilog Display tasks   Verilog Math Functions   Verilog Timeformat   Verilog Timescale Scope   Verilog File Operations

Code Examples   Hello World!

  Flops and Latches   JK Flip-Flop   D Flip-Flop   T Flip-Flop   D Latch

  Counters   4-bit counter   Ripple Counter   Straight Ring Counter   Johnson Counter   Mod-N Counter   Gray Counter

  Misc   n-bit Shift Register   Binary to Gray Converter   Priority Encoder   4x1 multiplexer   Full adder   Single Port RAM   Verilog Pattern Detector   Verilog Sequence Detector